Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) are two complementary strategies of performing input/output (I/O) between the central processing unit (CPU) and peripheral devices in a computer (typically mediating entry by way of chipset). Another method is using dedicated I/O processors, generally known as channels on mainframe computers, which execute their own directions. The memory and registers of the I/O devices are mapped to (associated with) deal with values, so a memory handle could check with either a portion of bodily RAM or to memory and registers of the I/O machine. Every I/O gadget either monitors the CPU's tackle bus and responds to any CPU access of an tackle assigned to that device, connecting the system bus to the specified machine's hardware register, or makes use of a dedicated bus. To accommodate the I/O gadgets, some areas of the address bus used by the CPU must be reserved for I/O and must not be out there for regular physical memory; the vary of addresses used for I/O devices is set by the hardware.

The reservation may be permanent, or momentary (as achieved via bank switching). An instance of the latter is found within the Commodore 64, which uses a form of memory mapping to trigger RAM or I/O hardware to seem in the 0xD000-0xDFFF range. Port-mapped I/O usually uses a special class of CPU directions designed specifically for performing I/O, such because the in and out directions discovered on microprocessors based on the x86 structure. Totally different varieties of these two instructions can copy one, two or 4 bytes (outb, outw and outl, respectively) between the EAX register or certainly one of that register's subdivisions on the CPU and a specified I/O port address which is assigned to an I/O machine. I/O devices have a separate deal with space from basic memory, both accomplished by an extra "I/O" pin on the CPU's bodily interface, or Memory Wave Workshop a complete bus dedicated to I/O. Because the address house for I/O is remoted from that for main memory, that is sometimes referred to as isolated I/O.

On the x86 architecture, index/knowledge pair is often used for port-mapped I/O. Totally different CPU-to-system communication methods, corresponding to memory mapping, don't affect the direct memory entry (DMA) for a system, as a result of, by definition, DMA is a memory-to-machine communication method that bypasses the CPU. Hardware interrupts are one other communication technique between the CPU and peripheral units, nonetheless, for plenty of causes, interrupts are at all times treated separately. An interrupt is machine-initiated, as opposed to the strategies talked about above, that are CPU-initiated. It is usually unidirectional, as information flows solely from device to CPU. Lastly, each interrupt line carries just one bit of information with a fixed which means, particularly "an occasion that requires consideration has occurred in a device on this interrupt line". I/O operations can slow memory access if the deal with and information buses are shared. This is because the peripheral system is normally much slower than fundamental Memory Wave Workshop. In some architectures, port-mapped I/O operates via a devoted I/O bus, alleviating the problem.

One merit of memory-mapped I/O is that, by discarding the extra complexity that port I/O brings, a CPU requires less inside logic and is thus cheaper, sooner, easier to construct, consumes much less energy and will be bodily smaller; this follows the essential tenets of reduced instruction set computing, and is also advantageous in embedded programs. The opposite benefit is that, because common memory instructions are used to handle gadgets, the entire CPU's addressing modes can be found for the I/O as properly because the memory, and instructions that carry out an ALU operation directly on a memory operand (loading an operand from a memory location, storing the end result to a memory location, or each) can be used with I/O machine registers as nicely. In distinction, port-mapped I/O directions are often very limited, usually offering only for Memory Wave easy load-and-retailer operations between CPU registers and that i/O ports, in order that, for instance, so as to add a relentless to a port-mapped system register would require three instructions: learn the port to a CPU register, add the constant to the CPU register, and write the consequence again to the port.