DFI - Ddr-phy.org
AUSTIN, Texas, Could 2, 2018 - The DDR PHY Interface (DFI) Group as we speak released model 5.Zero of the specification for interfaces between high-pace memory controllers and bodily (PHY) interfaces to support the requirements of future cell and server memory requirements. The DFI specifications, Memory Wave extensively adopted throughout the Memory Wave Method trade, allow greater interoperability. The DFI Group included several interface improvements on this newest specification. The new model of the specification adds protocol assist for the newest DDR and low-power memory applied sciences. Earlier versions of the specification defined memory training across the interface between the memory controller and the PHY. The new specification completely transitions to PHY-independent training mode where the PHY trains the memory interface without involving the controller. Different interface enhancements embrace decrease energy enhancements, offering a PHY-unbiased boot sequence, expanding frequency change support, and defining new controller-to-PHY interface interactions. "The industry is starting to embrace new low-energy and DDR memory applied sciences, including excessive-performance gadgets reminiscent of servers, storage, and networking; autonomous autos; and low-energy handheld units and IoT," acknowledged John MacLaren, DFI Group chairman and Cadence design engineering architect.
"The DFI Group, consisting of experts from main corporations in the trade, is enthusiastic to contribute to enabling this transition with the latest launch of the DFI specification. "Adopting open and normal interfaces like the new DFI 5.0 specification for top-velocity memory controller and PHY interface permits AMD to efficiently and successfully undertake new memory standards as we ship high-performance merchandise to our customers. "Cadence has been a key contributor to the DFI 5.0 customary, which helps to ensure interoperability between DDR PHYs and DDR controllers, notably for future memory devices," said Marc Greenberg, group director, product advertising and marketing, DDR, HBM, flash/storage and MIPI IP. "As a leading supplier of DDR IP and Verification IP, Synopsys makes important investments to make sure that our DesignWare
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